Impact of NBTI on digital integrated circuits in FinFET technologies

Abstract

In FinFET-based VLSI designs, heat issues from increase of driving current with temperature and self-heating effect profoundly influence the circuit performance and reliability. This work evaluates the performance of FinFET-based combinational circuits considering BTI stress and thermal effect of supply voltage and frequency variations. The proposed simulation framework is applied to selected benchmark circuits implemented with the 14-nm tri-gate bulk FinFET technology. The experimental results reveal that as temperature increases, BTI aging delay increasingly worsens, yet it is overridden by performance gain from the increase in driving current. We also prove that BTI degradation is dependent on power supply and frequency through their thermal impacts. Further, we introduce a DVFS based power reduction approach that scales down the supply voltage of hot circuits to maintain the performance. The results show that power reduction yielded from the proposed technique is larger for all circuits working at higher ambient temperature (as large as 66% in some experimental circuits working at 20 oC above the baseline ambient temperature) with a slight decrease in BTI degradation.